This invention relates, in general, to semiconductor devices, and more particularly, to an improved method of fabricating a BiCMOS integrated circuit having a high performance bipolar transistor.
When integrating bipolar transistors with CMOS transistors, compromises must be made to either the CMOS transistors or the bipolar transistors, or both, in order to integrate all the transistors on a single chip. Thus, any improvement which simplifies the BiCMOS fabrication process or improves the electrical characteristics of the transistors is desirable. Where NPN performance is heavily used, it is desirable to produce a bipolar which has a higher performance. In order to fabricate a high performance bipolar, it is essential to provide a minimum low current base resistance (R.sub.b) and minimum transistor junction capacitances. A lower base resistance will improve the switching speed of the bipolar transistor. It is also desirable to reduce the junction capacitances of the bipolar transistor, especially the base-collector (C.sub.bc), and the parasitic capacitances.
In terms of device fabrication, it is desirable to reduce the number of photolithography masks that are used in the process. This will allow for an improvement in device yield and a decrease in cycle time. In addition, it would be advantageous to be able to fabricate both NPN and PNP transistors on the same chip without many added masks or process steps. As technology enables the devices to be fabricated with smaller dimensions, it is desirable to make a bipolar transistor which is more scalable than in the past. A device is defined as being more scalable than another if it exhibits decreased sensitivity to drawn dimensions or lithographic tolerances.
By now it should be appreciated that it would be advantageous to provide an improved method of fabricating a high performance bipolar transistor that is also compatible with the method of fabricating MOS transistors.
Accordingly, it is an object of the present invention to provide an improved method of fabricating a BiCMOS integrated circuit having high performance bipolar transistors.
Another object of the present invention is to provide an improved method of fabricating a BiCMOS integrated circuit having bipolar transistors which have a reduced base resistance.
A further object of the present invention is to provide an improved method of fabricating a BiCMOS integrated circuit having high performance bipolar transistors which have improved switching speed.
Yet another object of the present invention is to provide an improved method of fabricating both vertical NPN and vertical PNP bipolar transistors integrated with CMOS transistors.
Still a further object of the present invention is to provide an improved method of fabricating bipolar transistors which have reduced collector to base capacitance.